A digital subscriber line (DSL) extends between a telephone service provider's central office and an end user's location. Typically, a plurality of DSLs lead to a single central office (CO). The physical termination at the central office is provided by a unit called a line card, which includes a plurality of processors, each of which is in charge of receiving and/or transmitting data signals along one of more of the lines. The signals may for example be according to a DMT (discrete multi-tone) standard protocol, such as DMT VDSL or DMT ADSL, in which case the processors may be referred to as DMT processing modules. In other DSL applications, a line card may be provided at customer premises equipment (CPE) or at a DLC (digital loop carrier) box where the analogue phone lines from multiple subscribers are combined to form a multiplexed signal, such as for transmission over an optical cable.
The VDSL and ADSL standards both operate based on a number of frequency-divided “channels” defined within the full range of frequencies, which can be transmitted over the DSL. On a given DSL there may thus be multiple channels, each generally associated with a direction along the DSL. Each of the channels is further divided into narrower frequency ranges known as “tones”. Data is transmitted on each channel using multiple tones within the channel. The data is coded in a format based on transmitting a series of “symbols” along the channel using substantially all the tones of the channel concurrently. Each symbol itself includes a number of “frames”.
The structure of part of the line card is shown schematically in FIG. 1. Within the line card are one or more DMT processing modules 1. Each DMT processing module 1 is associated with one or more corresponding DSL lines, and sends or receives data over a number of channels (each of which is a range of frequencies on one of the DSL lines). In FIG. 1, only a single DMT processing module 1 is shown, but there may in fact by any number. Also, the number of channels for the DMT processing module 1 is indicated as eight (labeled Ch1 to Ch8), but again there may be any number of such channels, possibly with a different number of channels for each DMT processing module 1. The DMT processing modules 1 each communicate with a “data link layer” processor 3 (also referred to as a “layer 2 processor”). The data link layer processor 3 in turn communicates over a “backbone” 9 to another location, typically using a packet- or cell-based communication protocols. Typical data link layer traffic protocols include ATM, POSPHY and Ethernet protocols. Thus, in one form the data layer link processor 3 may be an ATM processor or Ethernet processor. The data link layer processor 3 includes a master 5 and a buffer 7.
Although in FIG. 1, as noted above, only a single DMT processing module 1 is shown, if the data link layer processor 3 is an ATM, POSPHY or Ethernet processing module, there may be a plurality of DMT processing modules 1 connected to different respective ports of the data layer link processor 3, with all of the ports being connected in turn to the backbone 9 via a switching fabric of the data link layer processor 3 controlled by the master 5 and implemented using the buffer 7.
In the downstream (Tx) direction, cells or packets received from the backbone 9 are transmitted via the data link layer processor 3 to one (or possibly more) of the DMT processing modules 1, and the data within the cells or packets is extracted by that DMT processing module 1, converted by that DMT processing module 1 into the DSL communication format (which means encoding it into a symbol), and transmitted over one of that DMT processing module's corresponding DSLs. Conversely, in the upstream (Rx) direction, data received by one of the DMT processing modules 1 in the DSL protocol from along one of its corresponding DSL lines is extracted from the symbol (“decoding” the symbol), and converted by the DMT processing module 1 into packets or cells which the DMT processing module 1 transmits through the data link layer platform 3 to the backbone 9.
Each of the DMT processing modules 1 operates on a symbol-by-symbol basis, which requires that they have at least enough memory to store the whole of a symbol. The processing of this platform is “bursty” in nature since, for example in the Tx direction, it processes the entire symbol at once, and then waits until the symbol is sent over the DSL before processing the next. Conversely, when the DMT processing module 1 receives a symbol over the DSL line, large amount of data is transmitted to the data link platform 3. In a situation in which a single data link layer platform 3 is connected to multiple DMT processing modules 1, such as when the data link layer platform 3 is an ATM or POSPHY system, this traffic results in a particular port of the data link layer platform 3 becoming dominant. This problem is known as “cell burst” and affects the overall quality of service (QOS) of the system.
The traffic on the data link layer is less deterministic. This network traffic, whether it is ATM cells or Ethernet packets, is known to follow a Poisson distribution. This traffic appears “bursty” during a short period, but over a long period would have a constant rate. Note that the burstiness in the data link layer is different from that in the DMT processing modules, in the sense that the bursts (packets/cells) do not occur at regular intervals.
FIG. 2 shows schematically the timing of the communication between the data link platform 3 and one of the DMT processing modules 1 in a conventional device. FIG. 2 shows 8 upstream channels (or alternatively 8 downstream channels). This figure assumes that the DMT processing module 1 is operating 8 upstream channels, referred to as Ch1 to Ch8. The data link platform 3 continually polls the DMT processing module by sending it a polling enquiry signal, to determine whether it has generated any data for transmission to the data link platform 3. The data which the DMT processing module 1 sends to the layer 2 platform tell the layer 2 platform which channel the data came from.
FIG. 2 assumes the “worst case” scenario, that the DMT processing module 1 is receiving symbols over all 8 of the channels it is connected to. Accordingly, in response to each polling signal, the DMT processing module transmits a successive chunk of the data. The DMT processing module 1 transfers all the data received associated with one of the symbols (i.e., the data it has received on a given one of the channels) before moving onto the next channel. That is, starting at the a time t0, the DMT processing module 1 moves through all the eight channels in turn, and for each channel transmits successively all the packets it derives from the respective one of the received symbols. The total process takes a time referred to a “symbol period” (equal to the time between two locations on the time axis labeled to), which is composed of eight shorter periods during which communication in respect of only one of the channels occurs (this period is indicated for each channel by a respective shaded rectangle in FIG. 2). Note that whenever a symbol is received on a given channel, this results in an undesirable burst of data to one port of the data link layer platform 3. If symbols arrive on multiple channels (e.g., on all eight channels as shown in FIG. 2) then the burst is correspondingly greater.
A figure very similar to FIG. 2 can be drawn to represent the downstream traffic from the data link layer platform 3 to the DMT processing module 1. In this case, the data link layer platform 3, upon receiving data to be transmitted to one (or more) of the DSL lines, repeatedly polls the corresponding DMT processing module 1 to ask whether it is ready to receive data. The polling signal contains a different channel ID for different channels. In the case that a symbol is to be transmitted on a given channel, the DMT repeatedly sends a positive response, and, in response to each positive reply, receives a successive chunk of the data until the data link layer platform 3 has transmitted to it all the data associated with a given symbol.
The disadvantages arising from these various forms of burstiness can be at least partially ameliorated by ensuring that the buffer 5 if sufficiently large, but this approach has the disadvantage that the buffer becomes expensive to produce and consumes greater chip area.
Since space in the buffer 5 is limited, it is advantageous in the downstream direction for data to be transferred from the data link layer platform 3 to the DMT processing module(s) 1 as soon as possible. However, once this data has been transferred, the data link layer platform 3 may have no data left, and thus is forced to generate empty “idle cells” when the DMT processing module(s) request further data. These idle cells consume bandwidth between the DMT processing module(s) 1 and the data link layer platform 3 for no purpose, however, so from this point of view it would be advantageous if the data were transmitted as late as possible, to reduce the need for idle cells. In other words, there is an inherent contradiction between the need to transmit data as early as possible, and the need to transmit it as late as possible. Of course, if the data is left too long before being transmitted, then it may simply not be possible to transmit the data when it is required.
A need thus exists for an improved line card and methods for data communication with the line card that address the problems and defects of the prior art as described above. The present invention addresses these needs.